1 ? fn6255.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. isl34340 wsvga 24-bit long-reach video serdes with bidirectional side-channel the isl34340 is a serializer/deserializer of lvcmos parallel video data. the video data presented to the serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. it also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. ordering information features ? 24-bit rgb transport over single differential pair ? bidirectional auxiliary data transport without extra bandwidth and over the same differential pair ? 40mhz pclk transports - svga 800x600 @ 70fps, 16% blanking - wsvga 1024x600 @ 60fps, 8% blanking ? internal 100 termination on high-speed serial lines ? dc balanced 8b/10b line code allows ac-coupling - provides immunity against ground shifts ? transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates ? same device for serializer and deserializer simplifies inventory ?i 2 c interface ? high-speed serial lines meet 8kv esd rating ? pb-free (rohs compliant) applications ? navigation and display systems ? video entertainment systems ? industrial computing terminals ? remote cameras part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL34340INZ* ISL34340INZ -40 to +85 64 ld eptqfp q64.10x10b *add ?-t13? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl34340 isl34340 rgba/b/c pclk_in rgba/b/c ref_clk pclk_in vsync hsync dataen pclk_out vsync hsync dataen video_tx i2ca0 ref_res gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io video_tx i2ca0 ref_res gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io seriop serion seriop serion 27nf 27nf 27nf 27nf rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr 3.16 k 3.16 k 3.3v 1.8v vdd_io 3.3v 1.8v vdd_io vdd_io 10m differential cable 24 24 video source video sink vdd_io data sheet june 23, 2008 n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t i s l 3 4 3 4 1
2 fn6255.1 june 23, 2008 pinout isl34340 (64 ld eptqfp) top view block diagram 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rgbb3 rgbb1 rgbb0 rgba7 rgba6 rgba5 rgba4 rgba3 rgba2 rgba1 rgba0 pclk_out video_tx vdd_io gnd_cr gnd_cr vdd_cr vdd_cr dataen hsync vsync hsyncpol vsyncpol pclk_in gnd_p vdd_p scl sda i2ca2 i2ca3 rstb/pdb test_en status rgbc7 rgbc6 rgbc5 rgbc4 rgbc3 rgbc2 rgbc1 rgbc0 rgbb7 rgbb6 rgbb5 vdd_io rgbb4 i2ca1 i2ca0 test ref_res gnd_an vdd_an gnd_tx serion seriop gnd_tx vdd_tx gnd_cdr gnd_cdr vdd_cdr gnd_io vdd_cdr rgbb2 gnd_io 8b/10b x30 rgb v/h/de pclk_in (ref_clk when video_tx is lo) seriop serion sda 24 3 pclk_out 30 tx rx mux demux cdr vcm generator i 2 c scl pre- emphasis eq tdm ram video_tx (hi) isl34340
3 fn6255.1 june 23, 2008 absolute maximum rati ngs thermal information supply voltage vdd_p to gnd_p, vdd_tx to gnd_tx, vdd_io to gnd_io . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 4.6v vdd_cdr to gnd_cdr, vdd_cr to gnd_cr . . -0.5v to 2.5v between any pair of gnd_p, gnd_tx, gnd_io, gnd_cdr, gnd_cr . . . . . . . . . . . . . -0.1v to 0.1v 3.3v tolerant lvttl/lvcmos input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd_io + 0.3v differential input voltage . . . . . . . . . . . . . . .-0.3v to vdd_io + 0.3v differential output current . . . . . . . . . . . . . . short circuit protected lvttl/lvcmos outputs . . . . . . . . . . . . . . . . short circuit protected esd rating human body model all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kv seriop/n (all vdd connected, al l gnd connected) . . . . .8kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200v thermal resistance (typical, notes 1, 2) ja jc (c/w) eptqfp. . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. parameter symbol conditions min typ max units power supply voltage vdd_cdr, vdd_cr 1.7 1.8 1.9 v vdd_tx, vdd_p, vdd_an, vdd_io 3.0 3.3 3.6 v serializer power supply currents analog tx supply current i ddtx video_tx = 1 pclk_in = 40mhz 17 ma analog cdr supply current i ddcdr 57 ma digital i/o supply current i ddio 12ma digital supply current i ddcr 20 ma pll/vco supply current i ddp 17 ma analog bias supply current i ddan 5.5 ma total 1.8v supply current 77 90 ma total 3.3v supply current 40 46 ma deserializer power supply currents analog tx supply current i ddtx video_tx = 0 ref_clk = 40mhz 24 ma analog cdr supply current i ddcdr 45 ma digital i/o supply current i ddio 17 25 ma digital supply current i ddcr 32 ma pll/vco supply current i ddp 17 ma analog bias supply current i ddan 5.4 ma total 1.8v supply current 77 90 ma total 3.3v supply current 64 80 ma isl34340
4 fn6255.1 june 23, 2008 power-down supply current total 1.8v power-down supply current rstb = gnd; spec is per device 0.5 ma total 3.3v power-down supply current 1ma parallel interface high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input leakage current i in -10 0.01 10 a high level output voltage v oh i oh = -2.0ma, vdd_io = 3v 0.8*vdd_io v low level output voltage v ol i ol = 2.0ma, vdd_io = 3v 0.2*vdd_io v output short circuit current i osc 50 ma output rise and fall times t or /t of slew rate control set to min, c l = 8pf 1ns slew rate control set to max, c l = 8pf 4ns serializer parallel interface pclk_in frequency f in 640mhz pclk_in duty cycle t idc 40 50 60 % parallel input setup time t is 3.6 ns parallel input hold time t ih 1.6 ns deserializer parallel interface pclk_out frequency f out 640mhz pclk_out duty cycle t odc 50 % pclk_out period jitter (rms) t oj clock randomizer off 0.5 %t pclk pclk_out spread width t osprd clock randomizer on 20 %t pclk time to parallel output data valid t dv relative to pclk_out -4.7 5.5 ns deserializer output latency t cpd part-to-part, side-channel disabled 4 9 14 pclk deserializer reference clock (r ef_clk is fed into pclk_in) ref_clk lock time t pll 100 s ref_clk to pclk_out clock maximum frequency offset pclk_out is the recovered clock 1500 5000 ppm high-speed transmitter hs differential output voltage, transition bit vod tr txcn = 0x00 600 825 990 mv p-p txcn = 0x0f 1170 mv p-p txcn = 0xf0 975 mv p-p txcn = 0xff 1300 mv p-p hs differential output voltage, non-transition bit vod ntr txcn = 0x00 600 825 990 mv p-p txcn = 0x0f 460 mv p-p txcn = 0xf0 975 mv p-p txcn = 0xff 600 mv p-p electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. (continued) parameter symbol conditions min typ max units isl34340
5 fn6255.1 june 23, 2008 hs generated output common mode voltage v ocm 2.35 v hs common mode serializer-deserializer voltage difference v cm 20 120 mv hs differential output impedance r out 80 100 120 hs output latency t lpd part-to-part 4 7 10 pclk hs output rise and fall times t r/ t f 20% to 80% 150 ps hs differential skew t skew <10 ps hs output random jitter t rj 13.4 ps rms hs output deterministic jitter t dj 40 ps p-p high speed receiver hs differential input voltage v id 150 mv p-p hs generated input common mode voltage v icm 2.32 v hs differential input impedance r in 80 100 120 hs maximum jitter tolerance 0.52 ui p-p i 2 c i 2 c clock rate (on scl) f i2c 100 400 khz i 2 c clock pulse width (hi or lo) 1.3 s i 2 c clock low to data out valid 0 1 s i 2 c start/stop setup/hold time 0.6 s i 2 c data in setup time 100 ns i 2 c data in hold time 100 ns i 2 c data out hold time 100 ms electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. (continued) parameter symbol conditions min typ max units pin descriptions pin number pin name description serializer deserializer 52 to 63, 2 to 13 rgba[7:0], rgbb[7:0], rgbc[7:0] parallel video data lvcmos inputs parallel video data lvcmos outputs 22 hsync horizontal (line) sync lvcmos i nput horizontal (line) sync lvcmos output 23 vsync vertical (frame) sync lvcmos i nput vertical (frame) sync lvcmos output 21 dataen video data enable lvcmos input video data enable lvcmos output 26 pclk_in pixel clock lvcmos input pll reference clock lvcmos input 51 pclk_out default; not used recovered clock lvcmos output 41, 40 seriop, serion high speed differential serial i/o high speed differential serial i/o 24 hsyncpol cmos input for hsync 1: hsync is active low 0: hsync is active high 25 vsyncpol cmos input for vsync 1: vsync is active low 0: vsync is active high isl34340
6 fn6255.1 june 23, 2008 49 video_tx cmos input for video flow direction 1: video serializer 0: video deserializer 29, 30 sda, scl i 2 c interface pins (i 2 c data, i 2 c clk) 31 to 34 i2ca[3:0] i 2 c device address 16 rstb/pdb cmos input for reset and power-down. for nor mal operation, this pin must be forced high. when this pin is forced low, the device will be reset. if this pin stays low, the device will be in pd mode. 14 status cmos output for receiver status: 1: valid 8b/10b data received 0: otherwise note: serializer and deserializer switch roles during side-channel reverse traffic 36 ref_res analog bias setting resistor connection; use 3.16k 1% to ground 27 gnd_p pll ground 48, 64 gnd_io digital (parallel and control) ground 44, 45 gnd_cdr analog (serial) data recovery ground 39, 42 gnd_tx analog (serial) output ground 37 gnd_an analog bias ground 17, 18 gnd_cr core logic ground 19, 20 vdd_cr core logic vdd 43 vdd_tx analog (serial) output vdd 38 vdd_an analog bias vdd 46, 47 vdd_cdr analog (serial) data recovery vdd 1, 50 vdd_io digital (parallel and control) vdd 28 vdd_p pll vdd 15, 35 test_en, test must be connected to ground exposed pad exposed pad must be connected to ground notes: 3. pins with the same name are internally connected together. however, this connection must not be used for connecting together external components or features. 4. the various differently-named ground pins ar e internally weakly connect ed. they must be tied together externally. the differe nt names are provided to assist in minimizing the current loops involved in by passing the associated supply vdd pins. in particular, for esd testing, they should be considered a common connection. pin descriptions (continued) pin number pin name description serializer deserializer isl34340
7 fn6255.1 june 23, 2008 diagrams 0x00 0x0f 0xf0 0xff vod tr txcn vod ntr figure 1. vod vs txcn setting figure 2. parallel video input timing [hsyncpol = 0, vsyncpol = 0, pclkpol (reg) = 0] hsync vsync dataen pclk_in rgb[a:c][7:0] 1/f in t idc t is t ih t is t ih valid data valid data data ignored data ignored valid data video_tx = 1 isl34340
8 fn6255.1 june 23, 2008 applications overview a pair of isl34340 serdes transports 24-bit parallel video (16-bit parallel video for the isl34320) along with auxiliary data over a single 100 differential cable either to a display or from a camera. auxiliary da ta is transferred in both directions and can be used for remote configuration and telemetry. the benefits include lower emi, lower costs, greater reliability and space savings. the same device can be configured to be either a serializ er or deserializer by setting one pin (video_tx), simplifyi ng inventory. rgba/b/c, vsync, hsync, and dataen pins are inputs in serializer mode and outputs in deserializer mode. the video data presented to the serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. the side-channel data is transferred between the serdes pair during two lines of the vertical video blanking interval. when the side-channel is enabled, there will be a number of pclk cycles uncertainty from frame-to-frame. this should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. when properly configured, the se rdes link supports end-to-end transport with fewer than one error in 10 10 bits. differential signals and termination the isl34340 serializes the 24-bit parallel data at 30x the pclk_in frequency. the isl34320 serializes the 16-bit parallel data at 20x the pclk_in frequency. the extra 2 bits per word come from the 8b/10b encoding scheme. the high bit rate of the differential serial data requires special care in the layout of traces on pcbs, in the choice and assembly of connectors, and in the cables themselves. pcb traces need to be adjacent and matched in length (so as to minimize the imbalanced coupling to other traces or elements), and of a geometry to match the impedance of the transmitter and receiver, to mini mize reflections. similar care needs to be applied to the choice of connectors and cables. seriop and serion pins incorporate internal differential termination of the serial signal lines. external termination cannot be used unless the side-channel is disabled. serio pin ac-coupling ac-coupling minimizes the ef fects of dc common mode voltage difference and local power supply variations between two serdes. the serializer outputs dc balanced 8b/10b line code, which allows ac-coupling. the ac-coupling capacitor on serio pins must be 27nf on the serializer board and 27nf on the deserializer board. the value of the ac-coupling capacitor is very critical since a value too small will attenuate the high speed signal at low clock rate. a value too big will slow down the turn around time for the side-channel. receiver reference clock (ref_clk) the reference clock (ref_clk) for the pll is fed into pclk_in pin. ref_clk is used to recover the clock from the high speed serial stream. ref_clk is very sensitive to any instability. the following co nditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: ? ref_clk frequency must be within the limits specified ? ref_clk amplitude must be stable. a simple 3.3v cmos crystal oscillator can be used for ref_clk. power supply sequencing the 3.3v supply must be higher than the 1.8v supply at all times, including during power-up and power-down. to meet figure 3. parallel video output timing [hsyn cpol = 0, vsyncpol = 0, pclkpol (reg) = 0] hsync vsync dataen pclk_out rgb[a:c][7:0] 1/f out t odc t or t dv t of valid data valid data data held at previous value valid data t dv video_tx = 0 isl34340
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6255.1 june 23, 2008 this requirement, the 3.3v supply must be powered up before the 1.8v supply. for the deserializer, ref_cl k must not be applied before the device is fully powered up. applying ref_clk before power-up may require the deserializer to be manually reset. a 10ms delay after the 1.8v supply is powered up guarantees normal operation. power supply bypassing the serializer and deserializer functions rely on the stable functioning of plls locked to local reference sources or locked to an incoming signal. it is important that the various supplies (vdd_p, vdd_an, vdd_cdr, vdd_tx) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the pll to approaching the signal bit rate of the serial data. a combination of different values of capacitors from 1000pf to 5f or more with low esr characteristics is generally required. the parallel lvcmos vdd_io supply is inherently less sensitive, but since the rgb and sync/dataen signals can all swing on the same clock edge, the current in these pins and the corresponding gnd pins can undergo substantial current flow changes, so once again, a combination of different values of capacitors over a wide range, with low esr characteristics, is desirable. a set of arrangements of this type is shown in figure 4, where each supply is bypassed with a ferrite-bead-based choke, and a range of capacito rs. a ?choke? is preferable to an ?inductor? in this application, since a high-q inductor will be likely to cause one or more resonances with the shunt capacitors, potentially causing problems at or near those frequencies, while a ?lossy? choke will reflect a high impedance over a wide frequency range. the higher value capacitor, in particular, needs to be chosen carefully, with special care regarding its esr. very good results can be obtained with mu ltilayer ceramic capacitors, available from many suppliers, and generally in small outlines (such as the 1210 outline suggested in the schematic shown in figure 4), which provide good bypass capabilities down to a few m at 1mhz to 2mhz. other capacitor technologies may also be suitable (perhaps niobium oxide), but ?classic? electrolytic capacitors frequently have esr values of above 1 , that nullify any decoupling effect above the 1khz to 10khz frequency range. capacitors of 0.1f offer low impedance in the 10mhz to 20mhz region, and 1000pf capacitors in the 100mhz to 200mhz region. in general, one of the lower value capacitors should be used at each supply pin on the ic. figure 4 shows the grounding of the various capacitors to the pin corresponding to the supply pin. although all the ground supplies are tied together , the pcb layout should be arranged to emulate this arrangement, at least for the smaller value (high frequency) capacitors, as much as possible. i 2 c interface the i 2 c interface allows access to internal registers used to configure the serdes and to obtain status information. a serializer must be assigned a different address than its deserializer counterpart. the upper 3 bits are permanently set to 011 and the lower 4 bits determined by pins as follows: thus, 16 serdes can reside on the same bus. by convention, when all address pins are tied low, the device address is referred to as 0x60. scl and sda are open drain to allow multiple devices to share the bus. if not used, scl and sda should be tied to vdd_io. 0 1 1 i2ca3 i2ca2 i2ca1 i2ca0 r/w figure 4. power supply bypassing isl34340
10 fn6255.1 june 23, 2008 isl34340 thin plastic quad flatpack exposed pad plastic packages (eptqfp) d d1 a2 a1 11 o -13 o 11 o -13 o 0 o -7 o 0.020 0.008 min l 0 o min 0.25 0.010 gage plane e e1 -a- pin 1 -b- e -d- top view e2 bottom view d2 pin 1 ejector pin mark not pin #1 id ejector pin mark not pin #1 id ejector pin mark not pin #1 id q64.10x10b (jedec ms-026acd-hu issue d) 64 lead thin plastic quad flatpack exposed pad package symbol millimeters notes min max a-1.20- a1 0.05 0.15 - a2 0.95 1.05 - b 0.16 0.28 6 b1 0.17 0.23 - d 11.80 12.20 3 d1 9.90 10.10 4, 5 d2 3.46 3.76 - e 11.80 12.20 3 e1 9.90 10.10 4, 5 e2 3.46 3.76 - l 0.45 0.75 - n647 e 0.50 bsc - rev. 2 4/08 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toler ances per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. ?n? is the number of terminal positions. -c- -h- a plane b 0.004/0.008 0.09/0.20 with plating base metal seating 0.004/0.006 0.09/0.16 b1 0.003 0.08 a-b s d s c m 0.08 0.003 -c- -h-
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